| Syntax |
Description |
Operation |
Flags |
| ASR Rd |
Arithmetic Shift Right |
Rd(i) ← Rd(i+1) (n=0..6), C ← Rd(0) |
Z, C, N, V |
| LSL Rd |
Logical Shift Left |
Rd(i+1) ← Rd(i), Rd(0) ← 0, C ← Rd(7) |
Z, C, N, V |
| LSR Rd |
Logical Shift Right |
Rd(i) ← Rd(i+1), Rd(7) ← 0, C ← Rd(0) |
Z, C, N, V |
| ROL Rd |
Rotate Left trough Carry |
Rd(i+1) ← Rd(i), Rd(0) ← C, C ← Rd(7) |
Z, C, N, V |
| ROR Rd |
Rotate Right through Carry |
Rd(i) ← Rd(i+1), Rd(7) ← C, C ← Rd(0) |
Z, C, N, V |
| SWAP Rd |
Swap Nibbles |
Rd(3..0) ↔ Rd(7..4) |
— |
| Syntax |
Description |
Operation |
Flags |
| MOV Rd, Rr |
Copy Register |
Rd ← Rr |
— |
| MOVW Rd, Rr |
Copy Register Word |
R(d +1):Rd ← R(r+1):Rr |
— |
| LDI Rd, K |
Loads an 8 bit constant directly to register 16 to 31 |
Rd ← K |
— |
| LD Rd, X |
Load Indirect from Data Space to Register |
Rd ← [X] |
— |
| LD Rd, X+ |
Load Indirect from Data Space to Register with post-increment |
Rd ← [X], X ← X + 1 |
— |
| LD Rd, -X |
Load Indirect from Data Space to Register with pre-decrement |
X ← X - 1, Rd ← [X] |
— |
| LD Rd, Y |
Load Indirect from Data Space to Register |
Rd ← [Y] |
— |
| LD Rd, Y+ |
Load Indirect from Data Space to Register with post-increment |
Rd ← [Y], Y ← Y + 1 |
— |
| LD Rd, -Y |
Load Indirect from Data Space to Register with pre-decrement |
Y ← Y - 1, Rd ← [Y] |
— |
| LDD Rd, Y+q |
Load Indirect from Data Space to Register with offset |
Rd ← [Y+q] |
— |
| LD Rd, Z |
Load Indirect from Data Space to Register |
Rd ← [Z] |
— |
| LD Rd, Z+ |
КLoad Indirect from Data Space to Register with post-increment |
Rd ← [Z], Z ← Z + 1 |
— |
| LD Rd, -Z |
Load Indirect from Data Space to Register with pre-decrement |
Z ← Z - 1, Rd ← [Z] |
— |
| LDD Rd, Z+q |
Load Indirect from Data Space to Register with offset |
Rd ← [Z+q] |
— |
| LDS Rd, A |
Load Direct from Data Space |
Rd ← [A] |
— |
| ST X, Rr |
Store Indirect From Register to Data Space |
[X] ← Rr |
— |
| ST X+, Rr |
Store Indirect From Register to Data Space with post-increment |
[X] ← Rr, X ← X + 1 |
— |
| ST -X, Rr |
Store Indirect From Register to Data Space with pre-decrement |
X ← X - 1, [X] ← Rr |
— |
| ST Y, Rr |
Store Indirect From Register to Data Space |
[Y] ← Rr |
— |
| ST Y+, Rr |
Store Indirect From Register to Data Space with post-increment |
[Y] ← Rr, Y ← Y + 1 |
— |
| ST -Y, Rr |
Store Indirect From Register to Data Space with pre-decrement |
Y ← Y - 1, [Y] ← Rr |
— |
| STD Y+q, Rr |
Store Indirect From Register to Data Space with offset |
[Y+q] ← Rr |
— |
| ST Z, Rr |
Store Indirect From Register to Data Space |
[Z] ← Rr |
— |
| ST Z+, Rr |
Store Indirect From Register to Data Space with post-increment |
[Z] ← Rr, Z ← Z + 1 |
— |
| ST -Z, Rr |
Store Indirect From Register to Data Space with pre-decrement |
Z ← Z - 1, [Z] ← Rr |
— |
| STD Z+q, Rr |
Store Indirect From Register to Data Space with offset |
[Z+q] ← Rr |
— |
| STS A, Rr |
Store Direct to Data Space |
[A] ← Rr |
— |
| LPM |
Load Program Memory |
R0 ← {Z} |
— |
| LPM Rd, Z |
Load Program Memory |
Rd ← {Z} |
— |
| LPM Rd, Z+ |
Load Program Memory with post-increment |
Rd ← {Z}, Z ← Z + 1 |
— |
| ELPM |
Extended Load Program Memory |
R0 ← {RAMPZ:Z} |
— |
| ELPM Rd, Z |
Extended Load Program Memory |
Rd ← {RAMPZ:Z} |
— |
| ELPM Rd, Z+ |
Extended Load Program Memory with post-increment |
Rd ← {RAMPZ:Z}, Z ← Z + 1 |
— |
| SPM |
Store Program Memory |
{Z} ← R1:R0 |
— |
| IN Rd, P |
Load an I/O Location to Register |
Rd ← P |
— |
| OUT P, Rr |
Store Register to I/O Location |
P ← Rr |
— |
| PUSH Rr |
Push Register on Stack |
STACK ← Rr |
— |
| POP Rd |
Pop Register from Stack |
Rd ← STACK |
— |
| Syntax |
Description |
Condition |
Flags |
| BRBC s, A |
Branch if Bit in SREG is Cleared |
If SREG(S) = 0 |
— |
| BRBS s, A |
Branch if Bit in SREG is Set |
If SREG(S) = 1 |
— |
| BRCS A |
Branch if Carry Set |
If C = 1 |
— |
| BRCC A |
Branch if Carry Cleared |
If C = 0 |
— |
| BREQ A |
Branch if Equal |
If Z = 1 |
— |
| BRNE A |
Branch if Not Equal |
If Z = 0 |
— |
| BRSH A |
Branch if Same or Higher (Unsigned) |
If C = 0 |
— |
| BRLO A |
Branch if Lower (Unsigned) |
If C = 1 |
— |
| BRMI A |
Branch if Minus |
If N = 1 |
— |
| BRPL A |
Branch if Plus |
If N = 0 |
— |
| BRGE A |
Branch if Greater or Equal (Signed) |
If (N and V) = 0 |
— |
| BRLT A |
Branch if Less Than (Signed) |
If (N and V) = 1 |
— |
| BRHS A |
Branch if Half Carry Flag is Set |
If H = 1 |
— |
| BRHC A |
Branch if Half Carry Flag is Cleared |
If H = 0 |
— |
| BRTS A |
Branch if the T Flag is Set |
If T = 1 |
— |
| BRTC A |
Branch if the T Flag is Cleared |
If T = 0 |
— |
| BRVS A |
Branch if Overflow Set |
If V = 1 |
— |
| BRVC A |
Branch if Overflow Cleared |
If V = 0 |
— |
| BRID A |
Branch if Global Interrupt is Disabled |
If I = 0 |
— |
| BRIE A |
Branch if Global Interrupt is Enabled |
If I = 1 |
— |
| SBRC Rd, K |
Skip if Bit in Register is Cleared |
If Rd[K] = 0 |
— |
| SBRS Rd, K |
Skip if Bit in Register is Set |
If Rd[K] = 1 |
— |
| SBIC A, b |
Skip if Bit in I/O Registeris Cleared |
If I/O(A, b) = 0 |
— |
| SBIS A, b |
ПSkip if Bit in I/O Registeris Set |
If I/O(A, b) = 1 |
— |
