I was prompted to create this guide by the fact that all existing resources are inconvenient, since they do not have the ability to quickly switch between instructions. Whereas I wanted to be able to see the description of the command immediately after entering its name, without any unnecessary actions.

The manual is based on the Atmel documentation. In addition, more examples of the use of commands have been added here. In particular, examples for the AVR GCC assembler have been added, since the latter has a number of features related to linking the object code.

To quickly go to the required just, just enter its name.

Enter the instruction name in the input box above

Syntax | Description | Operation | Flags |
---|---|---|---|

AND Rd, Rr | Logical AND | Rd ← Rd and Rr | Z, N, V |

ANDI Rd, K | Logical AND with Immediate | Rd ← Rd and K | Z, N, V |

EOR Rd, Rr | Exclusive OR | Rd ← Rd xor Rr | Z, N, V |

OR Rd, Rr | Logical OR | Rd ← Rd or Rr | Z, N, V |

ORI Rd, K | Logical OR with Immediate | Rd ← Rd or K | Z, N, V |

COM Rd | One's Complement | Rd ← 0xFF - Rd | Z, C, N, V |

NEG Rd | Two's Complement | Rd ← 0 - Rd | Z, C, N, V, H |

CLR Rd | Clear Register | Rd ← Rd xor Rd | Z, N, V |

SER Rd | Set all Bits in Register | Rd ← 0xFF | — |

TST Rd | Test for Zero or Minus | Rd ← Rd and Rd | Z, N, V |

Syntax | Description | Operation | Flags |
---|---|---|---|

ADD Rd, Rr | Add without Carry | Rd ← Rd + Rr | Z, C, N, V, H |

ADC Rd, Rr | Add with Carry | Rd ← Rd + Rr + С | Z, C, N, V, H |

SUB Rd, Rr | Subtract without Carry | Rd ← Rd - Rr | Z, C, N, V, H |

SBC Rd, Rr | Subtract with Carry | Rd ← Rd - Rr - С | Z, C, N, V, H |

ADIW Rd, K | Add Immediate to Word | R(d+1):Rd ← R(d+1):Rd + K | Z, C, N, V, S |

SBIW Rd, K | Subtract Immediate from Word | R(d+1):Rdl ← R(d+1):Rd - K | Z, C, N, V, S |

SUBI Rd, K | Subtract Immediate | Rd ← Rd - K | Z, C, N, V, H |

SBCI Rd, K | Subtract Immediate with Carry | Rd ← Rd - K - С | Z, C, N, V, H |

INC Rd | Increment | Rd ← Rd + 1 | Z, N, V |

DEC Rd | Decrement | Rd ← Rd – 1 | Z, N, V |

MUL Rd, Rr | Multiply Unsigned | R1:R0 ← Rd * Rr | Z, C |

MULS Rd, Rr | Multiply Signed | R1:R0 ← Rd * Rr | Z, C |

MULSU Rd, Rr | Multiply Signed with Unsigned | R1:R0 ← Rd * Rr | Z, C |

FMUL Rd, Rr | Fractional Multiply Unsigned | R1:R0 ← (Rd * Rr) << 1 | Z, C |

FMULS Rd, Rr | Fractional Multiply Signed | R1:R0 ← (Rd * Rr) << 1 | Z, C |

FMULSU Rd, Rr | Fractional Multiply Signed with Unsigned | R1:R0 ← (Rd * Rr) << 1 | Z, C |

Syntax | Description | Operation | Flags |
---|---|---|---|

CBR Rd, K | Clear Bits in Register | Rd ← Rd and (0FFH – K) | Z, N, V |

SBR Rd, K | Set Bits in Register | Rd ← Rd or K | Z, N, V |

CBI P, b | Clear Bit in I/O Register | P.b ← 0 | — |

SBI P, b | Set Bit in I/O Register | P.b ← 1 | — |

BCLR s | Bit Clear in SREG | SREG.s ← 0 | SREG.s |

BSET s | Bit Set in SREG | SREG.s ← 1 | SREG.s |

BLD Rd, b | Bit Load from the T Flag in SREG to a Bit in Register | Rd.b ← T | — |

BST Rr, b | Bit Store from Bit in Register to T Flag in SREG | T ← Rd.b | T |

CLC | Clear Carry Flag | C ← 0 | C |

SEC | Set Carry Flag | C ← 1 | C |

CLN | Clear Negative Flag | N ← 0 | N |

SEN | Set Negative Flag | N ← 1 | N |

CLZ | Clear Zero Flag | Z ← 0 | Z |

SEZ | Set Zero Flag | Z ← 1 | Z |

CLI | Clear Global Interrupt Flag | I ← 0 | I |

SEI | Set Global Interrupt Flag | I ← 1 | I |

CLS | Clear Signed Flag | S ← 0 | S |

SES | Set Signed Flag | S ← 1 | S |

CLV | Clear Overflow Flag | V ← 0 | V |

SEV | Set Overflow Flag | V ← 1 | V |

CLT | Clear T Flag | T ← 0 | T |

SET | Set T Flag | T ← 1 | T |

CLH | Clear Half Carry Flag | H ← 0 | H |

SEH | Set Half Carry Flag | H ← 1 | H |

Syntax | Description | Operation | Flags |
---|---|---|---|

CP Rd, Rr | Compare two registers | If (Rd – Rr) | Z, N, V, C, H |

CPC Rd, Rr | Compare with Carry | If (Rd – Rr - C) | Z, N, V, C, H |

CPI Rd, K | Compare with Immediate | If (Rd – K) | Z, N, V, C, H |

CPSE Rd, Rr | Compare Skip if Equal | If (Rd = Rr) PC ← PC + 2 (or 3) | — |

Syntax | Description | Operation | Flags |
---|---|---|---|

ASR Rd | Arithmetic Shift Right | Rd(i) ← Rd(i+1) (n=0..6), C ← Rd(0) | Z, C, N, V |

LSL Rd | Logical Shift Left | Rd(i+1) ← Rd(i), Rd(0) ← 0, C ← Rd(7) | Z, C, N, V |

LSR Rd | Logical Shift Right | Rd(i) ← Rd(i+1), Rd(7) ← 0, C ← Rd(0) | Z, C, N, V |

ROL Rd | Rotate Left trough Carry | Rd(i+1) ← Rd(i), Rd(0) ← C, C ← Rd(7) | Z, C, N, V |

ROR Rd | Rotate Right through Carry | Rd(i) ← Rd(i+1), Rd(7) ← C, C ← Rd(0) | Z, C, N, V |

SWAP Rd | Swap Nibbles | Rd(3..0) ↔ Rd(7..4) | — |

Syntax | Description | Operation | Flags |
---|---|---|---|

MOV Rd, Rr | Copy Register | Rd ← Rr | — |

MOVW Rd, Rr | Copy Register Word | R(d +1):Rd ← R(r+1):Rr | — |

LDI Rd, K | Loads an 8 bit constant directly to register 16 to 31 | Rd ← K | — |

LD Rd, X | Load Indirect from Data Space to Register | Rd ← [X] | — |

LD Rd, X+ | Load Indirect from Data Space to Register with post-increment | Rd ← [X], X ← X + 1 | — |

LD Rd, -X | Load Indirect from Data Space to Register with pre-decrement | X ← X - 1, Rd ← [X] | — |

LD Rd, Y | Load Indirect from Data Space to Register | Rd ← [Y] | — |

LD Rd, Y+ | Load Indirect from Data Space to Register with post-increment | Rd ← [Y], Y ← Y + 1 | — |

LD Rd, -Y | Load Indirect from Data Space to Register with pre-decrement | Y ← Y - 1, Rd ← [Y] | — |

LDD Rd, Y+q | Load Indirect from Data Space to Register with offset | Rd ← [Y+q] | — |

LD Rd, Z | Load Indirect from Data Space to Register | Rd ← [Z] | — |

LD Rd, Z+ | КLoad Indirect from Data Space to Register with post-increment | Rd ← [Z], Z ← Z + 1 | — |

LD Rd, -Z | Load Indirect from Data Space to Register with pre-decrement | Z ← Z - 1, Rd ← [Z] | — |

LDD Rd, Z+q | Load Indirect from Data Space to Register with offset | Rd ← [Z+q] | — |

LDS Rd, A | Load Direct from Data Space | Rd ← [A] | — |

ST X, Rr | Store Indirect From Register to Data Space | [X] ← Rr | — |

ST X+, Rr | Store Indirect From Register to Data Space with post-increment | [X] ← Rr, X ← X + 1 | — |

ST -X, Rr | Store Indirect From Register to Data Space with pre-decrement | X ← X - 1, [X] ← Rr | — |

ST Y, Rr | Store Indirect From Register to Data Space | [Y] ← Rr | — |

ST Y+, Rr | Store Indirect From Register to Data Space with post-increment | [Y] ← Rr, Y ← Y + 1 | — |

ST -Y, Rr | Store Indirect From Register to Data Space with pre-decrement | Y ← Y - 1, [Y] ← Rr | — |

STD Y+q, Rr | Store Indirect From Register to Data Space with offset | [Y+q] ← Rr | — |

ST Z, Rr | Store Indirect From Register to Data Space | [Z] ← Rr | — |

ST Z+, Rr | Store Indirect From Register to Data Space with post-increment | [Z] ← Rr, Z ← Z + 1 | — |

ST -Z, Rr | Store Indirect From Register to Data Space with pre-decrement | Z ← Z - 1, [Z] ← Rr | — |

STD Z+q, Rr | Store Indirect From Register to Data Space with offset | [Z+q] ← Rr | — |

STS A, Rr | Store Direct to Data Space | [A] ← Rr | — |

LPM | Load Program Memory | R0 ← {Z} | — |

LPM Rd, Z | Load Program Memory | Rd ← {Z} | — |

LPM Rd, Z+ | Load Program Memory with post-increment | Rd ← {Z}, Z ← Z + 1 | — |

ELPM | Extended Load Program Memory | R0 ← {RAMPZ:Z} | — |

ELPM Rd, Z | Extended Load Program Memory | Rd ← {RAMPZ:Z} | — |

ELPM Rd, Z+ | Extended Load Program Memory with post-increment | Rd ← {RAMPZ:Z}, Z ← Z + 1 | — |

SPM | Store Program Memory | {Z} ← R1:R0 | — |

IN Rd, P | Load an I/O Location to Register | Rd ← P | — |

OUT P, Rr | Store Register to I/O Location | P ← Rr | — |

PUSH Rr | Push Register on Stack | STACK ← Rr | — |

POP Rd | Pop Register from Stack | Rd ← STACK | — |

Syntax | Description | Operation | Flags |
---|---|---|---|

RJMP A | Relative Jump | PC ← PC + A + 1 | — |

JMP A | Long Jump | PC ← A | — |

IJMP | Indirect Jump | PC ← Z | — |

EIJMP | Extended Indirect Jump | PC ← Z:EIND | — |

RCALL A | Relative Call to Subroutine | PC ← PC + A + 1 | — |

CALL A | Long Call to a Subroutine | PC ← A | — |

ICALL | Indirect Call to Subroutine | PC ← Z | — |

EICALL | Extended Indirect Call to Subroutine | PC ← Z:EIND | — |

RET | Return from Subroutine | PC ← STACK | — |

RETI | Return from Interrupt | PC ← STACK | I |

Conditional jumps to (PC ← PC + A + 1).

Syntax | Description | Condition | Flags |
---|---|---|---|

BRBC s, A | Branch if Bit in SREG is Cleared | If SREG(S) = 0 | — |

BRBS s, A | Branch if Bit in SREG is Set | If SREG(S) = 1 | — |

BRCS A | Branch if Carry Set | If C = 1 | — |

BRCC A | Branch if Carry Cleared | If C = 0 | — |

BREQ A | Branch if Equal | If Z = 1 | — |

BRNE A | Branch if Not Equal | If Z = 0 | — |

BRSH A | Branch if Same or Higher (Unsigned) | If C = 0 | — |

BRLO A | Branch if Lower (Unsigned) | If C = 1 | — |

BRMI A | Branch if Minus | If N = 1 | — |

BRPL A | Branch if Plus | If N = 0 | — |

BRGE A | Branch if Greater or Equal (Signed) | If (N and V) = 0 | — |

BRLT A | Branch if Less Than (Signed) | If (N and V) = 1 | — |

BRHS A | Branch if Half Carry Flag is Set | If H = 1 | — |

BRHC A | Branch if Half Carry Flag is Cleared | If H = 0 | — |

BRTS A | Branch if the T Flag is Set | If T = 1 | — |

BRTC A | Branch if the T Flag is Cleared | If T = 0 | — |

BRVS A | Branch if Overflow Set | If V = 1 | — |

BRVC A | Branch if Overflow Cleared | If V = 0 | — |

BRID A | Branch if Global Interrupt is Disabled | If I = 0 | — |

BRIE A | Branch if Global Interrupt is Enabled | If I = 1 | — |

SBRC Rd, K | Skip if Bit in Register is Cleared | If Rd[K] = 0 | — |

SBRS Rd, K | Skip if Bit in Register is Set | If Rd[K] = 1 | — |

SBIC A, b | Skip if Bit in I/O Registeris Cleared | If I/O(A, b) = 0 | — |

SBIS A, b | ПSkip if Bit in I/O Registeris Set | If I/O(A, b) = 1 | — |

Syntax | Description | Operation | Flags |
---|---|---|---|

NOP | No Operation | — | — |

SLEEP | Enter sleep mode | — | — |

WDR | Watchdog Reset | — | — |

BREAK | Break (for debuger) | — | — |